module Make: functor (Ast : Camlp4.Sig.Ast) -> sig .. end
functor (
Ast
:
Camlp4.Sig.Ast
) ->
sig
end
val print_interf : ?input_file:'a -> ?output_file:'b -> 'c -> 'd
?input_file:'a -> ?output_file:'b -> 'c -> 'd
val print_implem : ?input_file:'a -> ?output_file:'b -> 'c -> 'd